ADDR_WIDTH=S, SUFFIX_LEN=NONE, DATA_WIDTH=S, DUMMY_LEN=NONE, SUFFIX_WIDTH=S, DUMMY_WIDTH=S, PREFIX_LEN=NONE, PREFIX_WIDTH=S
Write transfer format configuration for memory address window 0.
Configure the bus width of each transfer phase individually, and configure the length or presence of the command prefix, command suffix and dummy/turnaround transfer phases. Only 24-bit addresses are supported.
The reset value of the M0_WFMT register is configured to support a basic 02h serial write transfer. However, writes to this window must first be enabled via the XIP_CTRL_WRITABLE_M0 bit, as XIP memory is read-only by default.
| PREFIX_WIDTH | The transfer width used for the command prefix, if any 0 (S): Single width 1 (D): Dual width 2 (Q): Quad width |
| ADDR_WIDTH | The transfer width used for the address. The address phase always transfers 24 bits in total. 0 (S): Single width 1 (D): Dual width 2 (Q): Quad width |
| SUFFIX_WIDTH | The width used for the post-address command suffix, if any 0 (S): Single width 1 (D): Dual width 2 (Q): Quad width |
| DUMMY_WIDTH | The width used for the dummy phase, if any. If width is single, SD0/MOSI is held asserted low during the dummy phase, and SD1…SD3 are tristated. If width is dual/quad, all IOs are tristated during the dummy phase. 0 (S): Single width 1 (D): Dual width 2 (Q): Quad width |
| DATA_WIDTH | The width used for the data transfer 0 (S): Single width 1 (D): Dual width 2 (Q): Quad width |
| PREFIX_LEN | Length of command prefix, in units of 8 bits. (i.e. 2 cycles for quad width, 4 for dual, 8 for single) 0 (NONE): No prefix 1 (8): 8-bit prefix |
| SUFFIX_LEN | Length of post-address command suffix, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) Only values of 0 and 8 bits are supported. 0 (NONE): No suffix 2 (8): 8-bit suffix |
| DUMMY_LEN | Length of dummy phase between command suffix and data phase, in units of 4 bits. (i.e. 1 cycle for quad width, 2 for dual, 4 for single) 0 (NONE): No dummy phase 1 (4): 4 dummy bits 2 (8): 8 dummy bits 3 (12): 12 dummy bits 4 (16): 16 dummy bits 5 (20): 20 dummy bits 6 (24): 24 dummy bits 7 (28): 28 dummy bits |
| DTR | Enable double transfer rate (DTR) for write commands: address, suffix and write data phases are active on both edges of SCK. SDO data is launched centre-aligned on each SCK edge, and SDI data is captured on the SCK edge that follows its launch. DTR is implemented by halving the clock rate; SCK has a period of 2 x CLK_DIV throughout the transfer. The prefix and dummy phases are still single transfer rate. If the suffix is quad-width, it must be 0 or 8 bits in length, to ensure an even number of SCK edges. |